1. Field of the Invention
The present invention relates to an amplification circuit, an amplification circuit noise reducing method and a program therefor, and particular, to a low-noise amplification circuit for radio communication front end created by using a digital CMOS device, a noise reducing method and a program for this amplification circuit.
2. Related Art
In accordance with the improvements in the mutual conductance and current gain cut off frequency due to the miniaturization developed in the CMOS manufacturing technology, the operational band and the noise characteristic of the CMOS circuit have been improved. As the result, a radio communication front end circuit, which had been traditionally manufactured with a compound semiconductor such as gallium arsenide or silicon-germanium, or a silicon bipolar device, can be manufactured by using a CMOS circuit. Particularly, a low-noise amplifier, which is an important block on determining the gain and noise characteristic of the entire radio receiving circuit, becomes possible to be manufactured on the same CMOS chip as a baseband logic. An example of a CMOS low-noise amplifier manufactured on the same chip as the baseband logic will be shown in FIG. 1.
In FIG. 8, an antenna 100, and a radio frequency band selecting filter and a transmission/reception switching device 101 are formed as off-chip elements 102, and subsequent elements from a low-noise amplifier are formed as on-chip elements.
A radio communication signal received by the antenna 100 is very weak, and at around the minimum reception sensitivity depending on the recent communication standard applied to the communication in which a digital modulation has been adopted, the amplitude of the signal is about several microvolts to several tens of microvolts.
The received signal power to the noise ratio has been improved in accordance with the improvement of the band use efficiency due to the development of the digital modulation technologies. However, the reflectance loss generated due to the impedance mismatch at an input unit of a receiving circuit has to be eliminated. Accordingly, when designing the CMOS low-noise amplifier, it is required to generate a high gain while preventing a heat noise from being generated at a circuit, with input being matched at on-chip.
In FIG. 8, an input matching unit 106 (a first order filter) is configured with such as an inductor A103, an inductor B104, and a capacitance C1 between a gate and a source of a transistor 105, to realize the matching with an output impedance of the off-chip side. And, by including an inductor C107 further, it is intended to enhance the gain and provide the frequency characteristic. However, when each of the inductors 103, 104, and 107 is fabricated on a silicon chip, it is formed in many cases with a spiral inductor whose low resistor wiring at the upmost layer is in a spiral shape. Here, a transistor 108 serves as an output switching.
Since an area of the spiral inductor is determined depending on an intended bandwidth (carrier wave frequency to be transmitted in an aerial, in the case of the low-noise amplifier) and is not reduced in accordance with the miniaturization of the CMOS device, the low-noise amplifier using many inductors becomes disincentive when the area of the chip is intended to be reduced for the radio communication circuit.
There is such a possibility that even the reduction in the chip cost due to the process for miniaturization cannot pay off the drastically increasing cost of the mask, which has become a problem, used in the miniaturization process, as a result of being restricted due to the inductor area.
When an alternate current frequency is ω, an impedance ZL generated particularly in an inductor L is expressed as ZL=jωL. For this reason, the inductance value L is required to be larger as the alternate current frequency ω (in the case of the low-noise amplifier, carrier wave frequency) is lower. As the result, the layout area of the inductor on the chip becomes greater as the frequency is in a lower band, and the reduction in the chip cost is suppressed more. Further, a wiring parasite resistance becomes greater, which has undesirable effects on the high frequency characteristic, such as deterioration in the noise characteristic and decrease in the gain.
Also, those inductors require a tuning step which is specific for an analog circuit typified by L and C combination, accompanied with repetition of a plurality of re-design and trial productions. In this regard, the development time and steps are required.
There is also an approach to realize high gain and frequency characteristic required for the low-noise amplifier by adding a negative feedback loop with the CMOS circuit, instead of tuning by the spiral inductor described above.
A configuration. shown in FIG. 9 is described in Non-Patent Document 1. In this example, the negative feedback is formed in such a manner that an amplification stage output from the CMOS low-noise amplifier configured with a transistor A201 and a transistor B202 is returned to an amplifier input h via a resistance R2 and a capacitance C2. This example shows that the frequency characteristic and the gain are changed according to the value of the resistance R2 at this time.
However, since the circuit configuring the feedback loop is an analog circuit and partly a passive element, there is such a problem that controlling the characteristic by an external signal is difficult. Further, though it is possible to reduce the chip area since this example doesn't use the spiral inductor or the like and it follows a process scaling of a digital CMOS device, an element, such as analog tuning between the transistor and the resistance R2, and between the transistor and the capacitance C2, still remains. Accordingly, problems such that the repetition of a plurality of re-design and trial productions is required, and a reconstruction of the characteristic after design is difficult, also inevitably remain.
In FIG. 9, if a circuit element which can be digitally-controlled easily, such as a filter for example, is added in the loop, it becomes possible to digitally-control the high frequency characteristic of the low-noise amplifier, which had been difficult to realize with the traditional art. According to this idea, however, a feedback configuration for variously changing the characteristic from the outside is to be added, and it carries a risk of oscillation. For this reason, a technique to suppress the risk of oscillation is required at the same time. As an example, by forcibly attenuating a signal to be fed back in particular so that the loop gain becomes to be equal to or less than one, the risk of oscillation due to the intensification of the input signal and the signal to be fed back can be suppressed.
As a digital type amplifier, as shown in Patent Document 1, a method with which, by splitting a signal wave having an envelope variation into two-types of the constant envelope modulated waves, amplifying and combining respective constant envelope modulated waves, an output amplitude of a signal wave having an envelope variation is amplified with relatively low-noise and low-deformation while maintaining the linearity, is reported.
Patent Document 1: Japanese Patent Application Laid-Open No. 01-284106
Non-Patent Document 1: Proceedings of 2006 IEEE International Solid-State Circuits Conference, description page, Section 200 and 201, 11.5